1. Bibliographic Information

• Title: Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization
• Authors: Linyong (Leo) Pang, Sha Lu, Michael Pomerantsev, Mariusz Niewczas, Kechang Wang, Bo Su, Michael Meyer, Aki Fujimura (from D2S, Inc.); Ezequiel Vidal Russell, Yang Lu, Michael Lee, Jennefir Digaum, Ming-Chuan Yang (from Micron Technology, Inc.). The collaboration between a computational lithography software company (D2S) and a leading semiconductor manufacturer (Micron) highlights the paper's focus on practical, production-oriented validation.
• Journal/Conference: Journal of Micro/Nanopatterning, Materials, and Metrology (JM3). This is a highly reputable peer-reviewed journal published by SPIE (the international society for optics and photonics), specializing in the fields of lithography and semiconductor manufacturing.
• Publication Year: 2024 (Published February 6, 2024).
• Abstract: The paper presents a full-chip, curvilinear, stitchless Inverse Lithography Technology (ILT) combined with Mask-Wafer Co-Optimization (MWCO). This approach is specifically designed to allow the resulting complex masks to be manufactured using common Variable-Shaped Beam (VSB) mask writers within a practical timeframe (under 12 hours). The authors validate the technology's benefits on physical masks and silicon wafers at Micron Technology. The method builds on previous work, which showed that curvilinear ILT could double the process window compared to standard OPC. This paper demonstrates that by using MWCO, these benefits can be achieved with VSB writers, which have historically been too slow for such complex patterns.
• Original Source Link: /files/papers/68ef3a06e77486f6f3192e87/paper.pdf. This is a formally published paper in a peer-reviewed journal.

2. Executive Summary

• Background & Motivation (Why):

  • Core Problem: In advanced semiconductor manufacturing, achieving high-fidelity patterns on a silicon wafer is extremely challenging due to optical physics limitations. Inverse Lithography Technology (ILT) is a powerful computational technique that calculates the ideal mask pattern to produce the desired wafer outcome, often resulting in complex, curvilinear (curvy) shapes. These curvilinear masks provide significantly larger and more robust process windows, which is critical for manufacturing yield.
  • Challenges: The adoption of full-chip curvilinear ILT has been blocked by two major hurdles:
    1. Computational Time: ILT calculations for an entire chip were historically too slow to be practical. This was largely solved by GPU-accelerated, stitchless approaches (as shown in the authors' 2019 work), but primarily for multibeam mask writers.
    2. Mask Write Time: The vast majority of mask manufacturing facilities use Variable-Shaped Beam (VSB) writers. These writers create patterns using rectangular "shots," and their write time is directly proportional to the number of shots. A complex curvilinear pattern, if naively translated into rectangles, would require an astronomical shot count, leading to impractically long write times (and high costs).
  • Innovation: This paper introduces Mask-Wafer Co-Optimization (MWCO) as the solution to the second hurdle. MWCO is a novel methodology that optimizes the VSB shots directly for the final wafer pattern quality, rather than trying to perfectly replicate an ideal curvilinear mask shape. This allows for a dramatic reduction in shot count, making VSB-based manufacturing of curvilinear ILT masks feasible.

• Main Contributions / Findings (What):

  • Practicality of Curvilinear ILT on VSB Writers: The paper demonstrates for the first time, with physical mask and wafer data, that full-chip curvilinear ILT masks can be written on standard VSB writers in a commercially viable timeframe of under 12 hours.
  • Superior Wafer Performance: The MWCO-enabled curvilinear ILT approach yields a 2x larger process window and a 3x reduction in critical dimension (CD) variation across different process conditions compared to the conventional Optical Proximity Correction (OPC) method of record.
  • Shot Count Efficiency: MWCO reduces the VSB shot count by over 4x compared to conventional fracturing methods for curvilinear patterns. The final shot count is shown to be comparable to, or even less than, that of standard OPC, eliminating the write-time penalty.
  • Workflow Paradigm Shift: The work proposes a fundamental change in the hand-off between the design/OPC team and the mask manufacturer. Instead of providing a file describing the desired mask shape, the design team provides a file describing the optimized mask shots, streamlining the process and embedding wafer-level optimization early in the flow.

3. Prerequisite Knowledge & Related Work

• Foundational Concepts:

  • Photolithography: The process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask (or reticle) to a light-sensitive chemical (photoresist) on a substrate (the silicon wafer).
  • 193i Lithography: A dominant technology for manufacturing advanced chips. It uses 193 nm deep-ultraviolet light, with a layer of purified water (immersion) between the lens and the wafer to improve resolution.
  • Optical Proximity Correction (OPC): A resolution enhancement technique where the photomask pattern is modified to compensate for distortions caused by diffraction and other process effects. For example, corners might be given "serifs" to prevent them from rounding on the wafer.
  • Inverse Lithography Technology (ILT): A more advanced and mathematically rigorous form of OPC. Instead of applying corrective rules to a design, ILT starts with the desired wafer shape and works backward ("inversely") to compute the optimal mask pattern that will produce it. This often results in non-intuitive, curvilinear shapes that offer the best possible performance.
  • Process Window (PW): The range of manufacturing parameters, primarily focus and exposure dose, within which the printed patterns on the wafer meet all specifications (like size and shape). A larger process window means the manufacturing process is more tolerant to variations and thus has a higher yield.
  • Variable-Shaped Beam (VSB) Mask Writer: A machine that writes patterns on a photomask using a focused beam of electrons. It projects rectangular or triangular "shots" of variable sizes. The total write time is proportional to the total number of shots. This is the most common type of mask writer in the industry.
  • Multibeam Mask Writer (MBMW): A newer generation of mask writer that uses thousands of parallel electron beams to write the pattern in a pixel-by-pixel fashion, similar to a dot-matrix printer. Its write time is largely independent of pattern complexity, making it ideal for curvilinear shapes but representing a significant capital investment.
  • Mask-Wafer Co-optimization (MWCO): The core technique of this paper. It is an optimization process that considers both the mask manufacturing constraints (e.g., VSB shots) and the final wafer printing outcome simultaneously. It directly optimizes the VSB shots to achieve the best wafer-level quality (e.g., lowest wafer Edge Placement Error).

• Previous Works & Technological Evolution: The paper builds directly on the authors' previous research, marking a clear evolutionary path:

  1. Challenge 1: ILT Computation Time: Traditionally, ILT was too slow for full-chip application and was limited to small, critical "hotspots."

  2. Solution (2019 SPIE Paper): The authors introduced TrueMask® ILT, a system using a novel GPU-accelerated architecture that emulates a single, giant computer. As shown in Figure 1, this "stitchless" approach avoids partitioning errors and makes full-chip curvilinear ILT computationally feasible in a single day. This work validated the massive (>100%) process window gains but relied on a multibeam mask writer.

     该图像是图1示意图，对比了三种ILT计算方法。传统方法将芯片分区，由多个CPU/GPU对处理，易产生拼接错误。D2S方法则通过多个CPU/GPU对模拟一个巨型CPU/GPU对，最终实现全芯片ILT，由一个模拟的巨型CPU/GPU对整体计算整个芯片，从而避免了拼接错误，提升了整体性。

  3. Challenge 2: VSB Write Time: The 2019 solution was not viable for the majority of mask shops equipped with VSB writers, as the shot count for the complex ILT patterns would be astronomical.

  4. Proposed Solution (2020 SPIE Paper & this Paper): The authors introduced MWCO to solve the VSB write time problem. This 2024 journal article provides the comprehensive validation of that method with extensive physical mask and wafer data.

• Differentiation: This work's primary differentiation is making the established benefits of full-chip curvilinear ILT accessible to the existing, widespread VSB mask manufacturing infrastructure. While prior work proved ILT's wafer-level benefits and solved the computation problem, this paper solves the critical manufacturing feasibility problem.

4. Methodology (Core Technology & Implementation)

The core of the paper is the Mask-Wafer Co-optimization (MWCO) methodology, which fundamentally changes the traditional manufacturing workflow.

• Principles: The central idea is to shift the optimization target. Instead of trying to create a mask that is a perfect geometric match to an ideal ILT pattern (minimizing mask EPE), MWCO directly optimizes the VSB shots to produce the best possible pattern on the final wafer (minimizing wafer EPE). This is effective because the lithography process acts as a natural low-pass filter; high-frequency details on the mask (like tiny "jogs" or stair-steps) are smoothed out. MWCO leverages this by finding a low-shot-count mask pattern that, while geometrically different from the ideal, produces an equivalent or better wafer image.

• Steps & Procedures: The traditional and MWCO workflows are contrasted in Figure 4.

  该图像是示意图，展示了(a)当前OPC与掩模工厂之间的掩模形状交接流程，以及(b)MWCO技术如何将交接点前移至掩模曝光图样。在(a)中，设计经OPC生成掩模形状，再在掩模工厂进行MPC和断裂处理得到掩模曝光图样。在(b)中，设计通过MWCO直接在OPC环节生成掩模曝光图样，随后在掩模工厂进行MPC修正。

  • Traditional Flow (Fig. 4a): The OPC shop generates a target mask shape (GDS/OASIS file). The mask shop then performs Mask Process Correction (MPC) and fractures this shape into VSB shots. The two steps are disconnected.

  • MWCO Flow (Fig. 4b): The OPC shop, using MWCO, directly generates an optimized list of VSB shots. The hand-off to the mask shop is the shot list itself, not a shape file.

    The detailed MWCO flow, shown in Figure 5, is as follows:

    该图像是图5，展示了用于可变形状束（VSB）掩模写入器的全芯片曲线型逆光刻技术（ILT）的掩模-晶圆协同优化（MWCO）流程。它从符合掩模规则的曲线型ILT生成开始，接着为VSB生成重叠的曝光区域，然后通过MWCO对曝光区域进行优化以减小晶圆边缘位置误差（EPE），最后将优化后的曝光区域输出到掩模工厂进行掩模制造。

  1. Full-Chip Curvilinear ILT Generation: The process begins with the GPU-accelerated TrueMask ILT platform to generate an ideal, stitchless, curvilinear target mask pattern that is compliant with mask manufacturing rules (MRC).
  2. Overlapping Shot Generation: To represent the curvilinear shapes efficiently, the system uses overlapping shots, especially for Sub-Resolution Assist Features (SRAFs). SRAFs are features on the mask that are too small to print on the wafer but help improve the print fidelity of the main features. Since SRAFs don't print, their exact shape is less critical, making them perfect candidates for this shot-count reduction technique. Main features are treated with more precision.
  3. MWCO Iterative Optimization: This is the key step. The system enters a loop that performs mask-wafer double simulation:
     • Mask Simulation: It simulates the actual, smooth contour that will form on the physical mask from the current set of VSB shots, accounting for e-beam and resist blur effects.
     • Wafer Simulation: It then takes this simulated mask contour and simulates the final pattern printed on the wafer.
     • Optimization: The algorithm measures the wafer EPE (the difference between the simulated wafer pattern and the desired target). It then adjusts the edges of the VSB shots to minimize this wafer EPE. This loop continues until the wafer EPE is minimized with an acceptable shot count.
  4. Output to Mask Shop: The final output is the optimized list of VSB shots. The mask shop can still run its own MPC using more accurate internal models, but the computationally expensive fracturing step is eliminated.

5. Experimental Setup

• Datasets:
  • Contact Array Sequence: A test pattern consisting of a 11x11 contact array repeated in 121 different configurations, with varying pitch and rotation angles. This comprehensive pattern covers a wide spectrum of feature densities, from dense to isolated, and tests the all-angle nature of the curvilinear solution.
  • Memory Patterns: For the main process window study, 61 challenging patterns commonly found in semiconductor memory applications were selected.
• Evaluation Metrics:
  • VSB Shot Count / Density: The primary metric for mask write time feasibility. Shot count is the total number of rectangular exposures. Shot density is $shots/µm²$. The paper uses a threshold of 36 shots/µm² as the criterion for a write time of less than 12 hours on a NuFlare EBM-9500 VSB writer.
  • Process Window (PW): The main indicator of manufacturing robustness.
    1. Conceptual Definition: The area on a Focus-Exposure Matrix (FEM) plot where the measured Critical Dimension (CD) of printed features falls within a specified tolerance (in this case, 10% of the target CD). A larger area signifies a better process.
    2. Experimental Method: Wafers were exposed at 7 different focus settings and 9 different dose settings, creating a 63-condition process matrix (as shown in Figure 16). CDs were measured at each condition to determine the passing region.
  • CD Variation: A measure of process-induced variability.
    1. Conceptual Definition: How much the size of a feature changes when process conditions (focus, dose) vary. Lower variation is better.
    2. Mathematical Formula: The paper uses Maximum CD - Minimum CD for each measured site across all 63 process conditions. $$\text{CD Variation} = \max_{i \in \{1, ..., 63\}}(\text{CD}_i) - \min_{i \in \{1, ..., 63\}}(\text{CD}_i)$$
    3. Symbol Explanation:
       • $\text{CD}_i$ is the Critical Dimension measured at the $i$-th process condition (a specific focus/dose pair).
• Baselines: The study compared four distinct approaches:
  1. Conventional OPC (POR): The standard Process of Record at Micron Technology.
  2. Curvilinear ILT with Conventional Shots: ILT fractured with non-overlapping shots (used to demonstrate the prohibitive shot count).
  3. Curvilinear ILT with Overlapping Shots (without MWCO): An intermediate method that uses overlapping shots to reduce shot count but optimizes for matching the ideal mask shape (mask EPE).
  4. Curvilinear ILT with Overlapping Shots and MWCO: The proposed full solution, optimizing for the final wafer result (wafer EPE).
• Hardware:
  • Mask Writer: NuFlare EBM-9500 PLUS (a VSB writer).
  • Lithography Process: Micron's 193i process.

6. Results & Analysis

• Core Results:

  • Shot Count and Write Time: Figure 10 shows that MWCO dramatically reduces the shot count for a complex contact array from over 1 million (conventional fracturing) to under 250k, which is comparable to the ~200k shots needed for much simpler OPC patterns. Figure 14 confirms this translates to a feasible write time; the shot density for MWCO remains consistently below the 36 shots/µm² threshold for a <12-hour write time, while conventional fracturing would be 5-10x slower.

    该图像是图10，展示了VSB光刻写入的散斑计数和散斑配置。图10(a)通过柱状图对比了不同方法（Conventional, Overlapping w/o MWCO, MWCO, OPC）的总散斑数量。图10(b)则以示意图形式呈现了三种接触阵列（Conventional Shots, Overlapping w/o MWCO Shots, MWCO Shots）的散斑配置，MWCO方法显示出更精简的配置。

    该图像是图14，展示了来自图11的接触阵列序列的VSB光刻写入的散斑密度（shot density）结果。图表对比了常规方法（Conventional）和掩模-晶圆协同优化（MWCO）方法。MWCO方法（蓝线）的散斑密度显著低于常规方法（红线），且始终保持在绿色虚线以下，表示写入时间少于12小时。常规方法在受SRAFs主导的区域散斑密度急剧增加，而MWCO方法则保持较低且稳定的散斑密度。

  • Mask and Wafer Quality: Figure 11 (mask SEMs) and Figure 15 (mask and corresponding wafer SEMs) provide visual proof. The VSB writer successfully fabricates the complex curvilinear patterns defined by the MWCO shot list. These masks, in turn, produce high-quality, uniform contact holes on the wafer across a variety of challenging pitches and orientations.

    该图像是图11的掩模扫描电镜图像，展示了三种接触阵列在不同可变形状电子束（VSB）曝光策略下的情况。其中，(a)列为传统曝光方式，(b)列为无掩模-晶圆协同优化（MWCO）的重叠曝光方式，而(c)列则采用了MWCO。图像清晰地对比了不同优化方案对掩模图案，尤其是曲线形状和接触孔形状的影响。

    该图像是图15，展示了MwCO（掩模-晶圆协同优化）在一个接触阵列上的结果。图中分(a)和(b)两列，(a)列显示了不同节距和方向的弯曲线形掩模设计MWCO VSB掩模SEM图像，其中可见复杂的掩模图案。与此对应，(b)列显示了这些掩模图案在晶圆上的SEM图像，清晰地呈现出印刷的圆形接触孔阵列。每对图像直观地对比了掩模设计与实际晶圆印制效果。

  • Process Window and CD Variation: This is the ultimate validation. Figure 18 shows that both curvilinear ILT methods reduce the average CD variation (Max - Min) across all process conditions by approximately 3x (from ~20 nm for OPC to ~7 nm). The process window plots in Figure 19 clearly show that the curvilinear ILT solutions (b and c) provide a green region (passing conditions) that is over 2x larger than that of conventional OPC (a), particularly in depth of focus.

    Fig. 18 is presented here as a summary; the original paper contains the full image.

    Fig. 19 is presented here as a summary; the original paper contains the full image.

• Ablations / Parameter Sensitivity: The comparison between "overlapping shots without MWCO" and "overlapping shots with MWCO" is a critical ablation study. Both significantly improve the process window over OPC. However, the MWCO version achieves a slightly better process window while using half the number of shots. This directly proves the value of co-optimizing for the wafer EPE rather than the mask EPE; it is both more effective and more efficient.

7. Conclusion & Reflections

• Conclusion Summary: The paper successfully demonstrates that the long-held vision of full-chip curvilinear ILT is now a practical reality for the entire semiconductor industry, not just those with the latest multibeam mask writers. The MWCO methodology overcomes the final barrier—prohibitive VSB write times—by intelligently co-optimizing the mask shots for the final wafer outcome. This enables a >2x process window enlargement and a 3x reduction in CD variation over standard OPC, using a mask that can be written on a VSB tool in under 12 hours with a shot count comparable to OPC. This technology completes the curvilinear ILT puzzle, making its benefits accessible to all advanced technology nodes.

• Limitations & Future Work:

  • The authors do not explicitly state limitations. However, the success of MWCO is heavily dependent on the accuracy of the mask and wafer simulation models. Any discrepancy between the models and physical reality could degrade the optimization.
  • The study focuses on 193i lithography for contacts/vias. Future work would involve extending this validation to more complex logic layers and applying the same principles to EUV lithography.

• Personal Insights & Critique:

  • Significance: This work represents a major breakthrough in computational lithography. The shift in workflow from a "mask shape" hand-off to a "mask shot" hand-off is a profound change that embodies the principles of Design-Technology Co-Optimization (DTCO). It tightly integrates design intent with manufacturing constraints.
  • Impact: This technology could significantly extend the capabilities and lifetime of 193i lithography, allowing companies to push performance on existing manufacturing lines without a full transition to EUV. For memory manufacturers like Micron, where highly regular patterns can greatly benefit from ILT, this provides a critical competitive advantage in yield and performance.
  • Critique: The paper is exceptionally strong due to its validation with extensive physical hardware data. The claims are well-supported by SEM imagery and robust statistical analysis of wafer measurements. While the specific algorithms within the TrueMask and MWCO software are proprietary, the principles and results are clearly presented, providing a compelling case for the technology's effectiveness and production-readiness.